The Fitter generates the following reports if you specify one or more settings that implement a specific feature in the Settings dialog box.
Summarizes infor. The clock delay controls provide a delayed signal on the global clock network from the dual-purpose clock pins. This report appears only if the design includes clock delay controls.
Reports register control signal path signal names, locations, fan-outs, and types for all clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, clear, read enable, write enable, and output enable signals used in the design.
Summarizes information about the delay chain Definition in your design. This report lists the node name and pin type. Delay chains are listed in terms of their delay chain fan-out setting and actual delay in ps.
Reports information regarding SERDES Definition receiver usagein device families with transceivers. The parameter values may include Name (the <SERDES receiver instance>), signal source names from Clock0, Enable0, Enable1, and Data Width. This report appears only if the design includes SERDES receivers.
Reports information regarding SERDES Definition receiver with dynamic phase alignment (DPA) Definition usage in device families with transceivers, including parameter values specified when instantiating the LVDS_RX. The parameter values may include Name (the <SERDES receiver instance>), signal source names from Clock0, Core Clock, Enable0, Data Realigner, Reset, DPLL Reset, Data Width, and FIFO (Enabled | Disabled). This report appears only if the design includes SERDES receivers.
Reports information regarding SERDES Definition transmitter usage in device families with transceivers, including parameter values you specified either by using the parameter editor, or by editing a text file. The parameter values may include Name (the <SERDES transmitter instance>), signal source names from Clock0, Enable0, and Data Width. This report appears only if the design includes SERDES transmitters.
Summarizes information about the parameter settings for each delay-locked loop (DLL) Definition. One row is included for each DLL atom. The report includes the following information:
Summarizes information about the parameter settings for each DQS I/O Definition I/O pin or nDQS I/O pin in your design. This report appears only if your design targets a supported device(ArriaIIseries, Stratix IV, and Stratix V) family for compilation.
Reports information regarding usage of DSP block Definition. This section is omitted if the design does not include DSP blocks. The report includes the following information:
·Name shows the name of the node contained in a DSP block.
·Mode shows the mode in which the DSP block is operating
·Location shows the location on the DSP block where the instance is located.
·Sign Representation shows the sign representation of the DSP block.
·Register(s) lists all the registers available for the DSP block and whether or not they were used. Types of registers can include:
oData Input registers
oPipeline registers
oOutput registers
·Input Cascadedindicatesthe use of input shift register chains in the DSP block.
·Has Output Adder Chain shows the use of output adder chains in the DSP block.
Reports information about the embedded cells in the device. The report lists the following information:
This section is omitted if the design does not include DSP blocks. The report lists the following information:
Summarizes information about the modes usable by DSP block Definition. These modes can include:
·Independent 9x9
·Independent 18x18 packed
·Independent 18x18
·Independent 18x18 with 32-bit result
·Independent 18x18 plus 36
·Sum of two 18x18 with systolic register
·Sum of four 18x18
·Sum of two 18x18
·Complex 25x18
·Independent 27x27
·Sum of two 27x27
·Sum of two 36x18
·Integer 36x36 / Complex 18x18
·Independent 36x18
·Independent 54x54
·Independent 72x18
·Floating Point Multiplier
·Floating Point Adder
·Floating Point Addition of Products
·Floating Point Accumulation of Products
·Floating Point Vector Mode 1
·Floating Point Vector Mode 2
Summarizes information about the RAM memory blocks in the design, including name, mode, location, port width, port depth, size, the number of RAM memory blocks used to implement the memory, and the Memory Initialization File (.mif) Definition, if a Memory Initialization File was specified for the initial contents of the memory.
The Fitter Resource Usage Summary report and the Fitter RAM Summary report both report information about RAM memory blocks, but the values reported may differ. The Fitter Resource Usage Summary report shows the number of packed RAM memory blocks, which equals the number of blocks actually used. The Fitter RAM Summary report shows a count of each user-instantiated logical memory blocks and the number of spread out RAM memory blocks. Because a physical memory block can be used by more than one logical memory block through packing, the Fitter RAM Summary report shows a Location column, indicating where multiple logical memories are used. The report lists the following information:
Reports global and dedicated fast input signal paths by their signal names, locations, and fan-outs; identifies whether the particular signal is global; and specifies the global resource used.
Summarizes information about the gigabit transceiver block (GXB) Definition receiver, including the name, data rate, and receiver channel location of each channel.
Summarizes information about the gigabit transceiver block (GXB) Definition transmitter including the name, data rate, and receiver channel location of each channel. This report appears only if the design targets a supported device(AriaIIseries, CycloneIV, and StratixIV GX) for compilation.
Reports information about the gigabit transceiver block (GXB) Definition receiver channel use, implemented with the alt2gxb megafunction. The report includes parameter values you specified with the parameter editor or by editing a text file. This report appears only if you specified a device with transceivers and the design includes GXB transmitter PLL & GXB receiver PLL Definition.
Reports information about the gigabit transceiver block (GXB) Definition transmitter channel use, which is implemented with the the alt2gxb megafunction. The report includes parameter values you specified with the parameter editor or by editing a text file. This report appears only if you specified a device with transceivers and the design includes GXB transmitter PLL & GXB receiver PLL Definition.
Reports information about GXB transmitter PLL & GXB receiver PLL Definition including the name of the transmitter PLL, output clock frequency, in clock frequency; multiply by and divide by factors; PLL type, VCO range and location in the design.
Reports information about central clock dividers, including the digital reference clock output frequency and core clock output frequency; the divide by factor; the status of the digital reference clock post divider and core clock output post divider, the PCIE x8 receiver mode, and the location in the design.
Reports the amount of trace delay compensation recommended for each LVDS node in a design with dynamic phase alignment turned off that targets a device containing transceivers.
The report lists the node name, pin, a recommendation for additional trace delay in ps, and the estimated TCCS reduction in ps.
Reports a list of the 50 highest fan-out signals that are non-global in the design, in descending order. This report provides information regarding the high fan-out signals in the design that may be difficult to route.
Reports information about the pad-to-core delay chain fan-out for the device. This report appears only if the design includes delay chain Definition. The report lists the following information:
Summarizes information about enhanced PLL Definition in Cyclone and Stratix series devices, and enhanced PLL Definition and fast PLL Definition in supported device(ArriaIIseries, StratixIV, and StratixV) families. This report appears only if the design includes PLLs. The report lists the following information:
Reports usage information about enhanced PLL Definition in Cyclone and Stratix series devices, and enhanced PLL Definition and fast PLL Definition in supported device(ArriaIIseries, StratixIV, and StratixV) families. This report lists the values of the specific output clock(s) for the PLLs in the design. This report appears only if the design includes PLLs. The report lists the following information: