Analysis & Synthesis Summary Reports

Summarizes the following information about the compilation:

• Analysis & Synthesis Status shows the status (Successful | Unsuccessful), end date, and end time of Analysis & Synthesis.
• Quartus^® Prime Standard Edition Version shows the current version of the Quartus^® Prime Standard Edition software.
• Revision Name shows the revision name specified in the Revisions dialog box.
• Top-Level Entity Name
• Family shows the device family name specified in the Device page of the Settings dialog box.
• Logic Utilization shows the total percent of logic used. Appears only if you specified a supported device family for compilation. The number is a total of Combinational ALUTs, Memory ALUTs, Logic registers or Dedicated logic registers, depending upon the device you specified for compilation.
• Logic utilization (in ALMs) shows the number ofAdaptive Logic Modules (ALMs) needed in designs targeting supported devices.
• Total registers shows the total number of registers used. This information appears only if you specified a supported device family for compilation.
• Total logic elements shows the total number of logic elements used. This information only appears if you specified a supported device family for compilation. This information includes Total combinational functions and Dedicated logic registers for devices.
• Total pins shows the total number of pins used and the total number of pins available.
• Total virtual pins shows the total number of virtual pins used.
• Total block memory bits shows the total number of block memory bits used. This information appears only if you specified a StratixIII device for compilation.
• Total memory bits shows the total number of memory bits used and the total number of memory bits available. The total number of memory bits available is the total number of memory buts in the and memory blocks and M-RAM Definition in a supported device family, or the total number of memory bits available in the M4K memory blocks.
• DSP block 9-bit elements shows the total number of DSP block Definition 9-bit elements used. DSP block 9-bit elements make up the DSP blocks in a supported device family.
• DSP block 18-bit elements shows the total number of DSP block Definition 18-bit elements used. DSP block 18-bit elements make up the DSP blocks.
• Embedded multiplier block 9-bit elements shows the total number of multiplier block Definition 9-bit elements used. Embedded multiplier block 9-bit elements make up the multiplier blocks in a CycloneIII device.
• Total GXB Receiver Channels shows the number of channels used in a design targeting a supported device family.
• Total GXB Receiver Channels PCS shows the number of physical coding sub-layer channels used in a design targeting a supported device family.
• Total GXB Receiver Channels PMA shows the number of physical media attachment channels used in a design targeting a supported device family.
• Total GXB Transmitter Channels shows the number of channels used in a design targeting a supported device family.
• Total GXB Transmitter Channel PCS shows the number of physical coding sub-layer channels used in a design targeting a supported device family.
• Total GXB Transmitter Channel PMA shows the number of physical media attachment channels used in a design targeting a supported device family.
• Total HSSI 8G RX PCSs shows the number of high speed serial interface physical coding sub-layer receiver channels operating at 8GHz. in a design targeting a StratixV device.
• Total HSSI 10G RX PCSs shows the number of high speed serial interface physical coding sub-layer receiver channels operating at 10GHz in a design targeting a StratixV device.
• Total HSSI PMA RX Deserializers shows the number of high speed serial interface physical media attachment receiver channels in a design targeting a StratixV device.
• Total HSSI 8G TX PCSs shows the number of high speed serial interface physical coding sub-layer transmitter channels operating at 8GHz. in a design targeting a StratixV device.
• Total HSSI 10G TX PCSs shows the number of high speed serial interface physical coding sub-layer transmitter channels operating at 10GHz in a design targeting a StratixV device.
• Total HSSI PMA TX Serializers shows the number of high speed serial interface physical media attachment transmitter channels.
• Total HSSI CDR PLLs shows the number of high speed serial interface clock data recovery PLLs in a design targeting a StratixV device.
• Total PLLs shows the total number of Phase-Locked Loop (PLL) Definition used.
• Total DLLs shows the total number of delay-locked loop (DLL) Definition used. This information appears only if you specified a supported device for compilation.

Reports messages generated by Analysis & Synthesis during the current process. Analysis & Synthesis generates info, warning, and error messages that report conditions observed during the Analysis & Synthesis process.

You can right-click a message in the Analysis & Synthesis Messages report and click Help to display help on the selected message, or click Locate to view a list of options available for the selected message.