Analysis & Synthesis Formal Verification Reports

Lists the entities that Quartus^® Prime Standard Edition Integrated Synthesis automatically converted to black-box entities in the design. Quartus^® Prime Standard Edition Integrated Synthesis automatically converted any megafunction or library of parameterized modules (LPM) function without a formal verification model to a black-box entity. The report contains the following information:

• Entity Nameshows the name of the entity converted to a black-box entity.
• File Name shows the name of the Verilog HDL or VHDL design file that contains the entity.
• Line # shows the line number in the Verilog HDL or VHDL design file that contains the entity.

Lists the inferred RAM instance(s) that Quartus^® Prime Standard Edition Integrated Synthesis recommends be converted to a black-box entity or instantiated with the IP Catalog. If the Auto RAM Replacement logic option is turned on, the Quartus^® Prime Standard Edition software automatically recognizes RAM logic and infers the appropriate megafunction. The report contains the following information:

• Design Logic shows the instance name of the inferred RAM block.
• RAM Type shows the type of the inferred RAM block.
• File Name shows the name of the HDL file that contains the instance.
• Line # shows the line number in the HDL file that contains the instance.

Lists the inferred ROM instance(s) that Quartus^® Prime Standard Edition Integrated Synthesis recommends be converted to a black-box entity or instantiated with the IP Catalog. Normally, the ROM is inferred (if the Auto ROM Replacement logic option is turned on), but the Quartus^® Prime Standard Edition software did not infer the ROM, which could cause verification mismatches in the Incisive Conformal software. The report contains the following information:

• Design Logic shows the instance name of the inferred ROM block.
• Number of Stored Words shows the number of words stored in memory.
• Width of Input Port shows the width, in bits, of the input port.
• ROM Type shows the type of the inferred ROM block.
• File Nameshows the name of the HDL file that contains the instance.
• Line # shows the line number in the HDL file that contains the instance.

Lists the inferred shift register instance(s) that Quartus^® Prime Standard Edition Integrated Synthesis recommends be converted to a black-box entity or instantiated with the IP Catalog. Normally, the shift register is inferred (if the Auto Shift Register Replacement logic option is turned on), but the Quartus^® Prime Standard Edition software did not infer the shift register, which could cause verification mismatches in the Incisive Conformal software. The report contains the following information:

• Register Name shows the instance name of the inferred shift register.
• Number of Taps shows the number of regularly spaced taps along the shift register.
• Tap Distance shows the distance between the regularly spaced taps in clock cycles. This number translates to the number of RAM words used.
• Width shows the width of the input pattern.
• File Name shows the name of the HDL file that contains the instance.
• Line # shows the line number in the HDL file that contains the instance.

Lists information about a single state machine in the design, including encoding, state values, and bit values.

Lists information regarding the logic cells used by Quartus^® Prime Standard Edition Integrated Synthesis to represent combinational loops in the design. Combinational loops may result in verification mismatches when performing formal verification. The report contains the following information:

• Name of Logic Cell Representing Combinational Loop shows the instance name of the logic cell.
• Name of Logic Cell Driver shows the name of the signal feeding the inserted logic cell.

Lists the instance names of latches inferred in the design by Quartus^® Prime Standard Edition Integrated Synthesis. Quartus^® Prime Standard Edition Integrated Synthesis automatically infers latches from some HDL constructs that result in combinational loops in the design. Combinational loops may result in mismatches when performing formal verification.

Lists the registers in the design merged by Quartus^® Prime Standard Edition Integrated Synthesis. Quartus^® Prime Standard Edition Integrated Synthesis may merge duplicate registers during synthesis, for example, to optimize the area of a design. Register merging may lead to mismatches when performing formal verification. The report lists the Original Register Name and the resulting Merged Register Name.

Lists the Register Name of registers with input signals stuck at GND or VCC removed by Quartus^® Prime Standard Edition Integrated Synthesis, and the Value (GND or VCC) of the stuck input signal. Removed registers may cause mismatches or unmapped points when performing formal verification.

Lists the registers in the design duplicated by Quartus^® Prime Standard Edition Integrated Synthesis. Quartus^® Prime Standard Edition Integrated Synthesis may duplicate registers during synthesis; for example, if you specify the Maximum Fan-Out logic option for a node, the Quartus^® Prime Standard Edition software duplicates the registers to reduce the number of fan-outs from the node. Register duplication may lead to mismatches when performing formal verification. The report lists the Original Register Name and the Duplicated Register Name.