Status Window

Full Compilation / Compile & Simulate

The total progress of all processes carried out for the compilation or for the compilation and simulation shown in percentage of completion and elapsed time.

Analysis & Synthesis

The Compiler module that generates a single project database integrating all the design files in a design, performs logic synthesis to minimize the logic of the design, and performs technology mapping to implement the design logic.

Assembler

The Compiler module that creates one or more programming files for programming or configuring the device(s) for a project.

Check Netlist

The Compiler module that checks the netlist.

Database Export

The command used for exporting a database from a project.

Database Import

The command used for importing a database into a project.

Design Assistant

The Compiler module that checks the reliability of the design based on a set of design rules.

EDA Netlist Writer

The Compiler module that generates output netlist files for use with other EDA tools.

EDA Physical Synthesis Tool

The module that performs physical synthesis with other EDA tools.

EDA Simulator

The module that runs an EDA simulation tool automatically after compilation from within the Quartus^® Prime Standard Edition software without recompiling the design.

EDA Synthesis Tool

The module that runs an EDA synthesis tool from within the Quartus^® Prime Standard Edition software.

Fitter

The Compiler module that fits the logic of a project into one or more devices.

Functional Simulation Netlist Generation

The Compiler module that generates a netlist for functional simulation.

RTL Viewer Preprocess

The module that allows you to view a schematic of the internal structure of the design netlist.

Simulator

The module that simulates the design.

Technology Map Viewer Preprocess

The module that allows you to view a schematic of the internal structure of the design netlist, as well as timing information.

Test Bench Template Writer

The Compiler module that generates a template for a test bench file.

TimeQuest Timing Analyzer

An ASIC-style, advanced timing analysis tool that uses industry standard constraint, analysis, and reporting methodology. Offers GUI or command-line interface using Synopsys Design Constraints File (.sdc) Definition format

Timing Analyzer

The Compiler module that computes delays for the given design and device and annotates them on the netlist for subsequent use by the Simulator or the Compiler.

VQM Writer

The module that the runs the Compiler database interface and saves intermediate synthesis results into a Verilog Quartus Mapping File (.vqm).