A configuration scheme in which an external controller, such as a CPU, loads the design data into an Altera device supported by the Quartus® Prime Standard Edition software except MAX II devices via a common data bus. Data is latched by the device on the first rising edge of a CPU-driven clock signal. The next eight falling clock edges serialize this latched data within the device. The device latches the next 8-bit byte of data on every eighth rising edge of the clock signal until the device is completely configured.