The Logic Analyzer Interface Editor helps you debug your design in the device using an external logic analyzer. With the Logic Analyzer Interface Editor you can debug a large set of nodes using only a small number of output pins, and you can connect multiple nodes to one output pin while the device is running in the system. The Logic Analyzer Interface Editor gives you great flexibility in viewing and editing how the nodes are connected to the output pins. It adds minimal logic to your design such that the placement and routing of the original design are not changed significantly, especially in the incremental compilation mode. Also, you can debug your design on your external logic analyzer in timing mode.
In the debugging phase of your project, you have the choice of using the embedded logic analyzer, the SignalTap II Logic Analyzer, or connecting an external logic analyzer to the device and reading the output of nodes with the Logic Analyzer Interface from the output pins to the analyzer. You can use the SignalTap II Logic Analyzer when physical access for connecting probes to output pins is limited. The external logic analyzer, however, provides you with more flexibility, allowing you to use greater sampling depth and triggering options of your external logic analyzer.