Setting Up the SignalTap II Logic Analyzer

You can set up the SignalTap II Logic Analyzer to capture signals from internal device nodes while the device is running at full speed so that you can debug your design. The SignalTap II Logic Analyzer allows you to use an existing SignalTap II Files (.stp)) to run an analysis, or you can create a new SignalTap II File, and make changes as needed. Also, you can create and instantiate one or more instances of a megafunction in the design without a SignalTap II File as follows:

IP Catalog Name

IP Core

SignalTap II Logic Analyzer (JTAG-accessible Extensions)

sld_signaltap

Multiple instances of the SignalTap II Logic Analyzer can be set up to run concurrently in your design, and you can assign different settings to each instance, which allows you to collect and analyze different sets of data when debugging your design. You trigger the SignalTap II Logic Analyzer to capture data according to the conditions you have set up. Basic triggering allows you to describe a logic event with logic conditions for signals. Advanced triggering allows you to describe more complex trigger conditions such as comparison, logical, and reduction operators. You trigger the SignalTapII Logic Analyzer when input signals match the basic trigger pattern. You can begin capturing data when the device first receives power. You can control the parameters for performing the triggering operation from within the SignalTap II Logic Analyzer with an editor and selecting standard logical objects from the included library.

Note: Before working with the SignalTap II Logic Analyzer, you must perform Analysis & Elaboration, perform Analysis & Synthesis, compile the design, create a SignalTap II file, and open the SignalTap II Logic Analyzer window.