Running the SignalTap II Logic Analyzer

You can attach SRAM Object Files (.sof) to SignalTap II Files (.stp)to load configuration data, which allows you to have multiple SignalTap II configurations for triggering. You can add, remove, rename, or extract SRAM Object Files, providing further analysis capabilities when programming a device. The SignalTap II Logic Analyzer also allows you to specify parameters for acquiring data after you set up triggering conditions. You can select whether to route the data from the device's memory blocks to the SignalTap II Logic Analyzer via the JTAG port, or to the I/O pins for use by an external logic analyzer or oscilloscope.

Note: Before working with the SignalTap II Logic Analyzer, you must perform Analysis & Synthesis and Analysis & Elaboration on the design, compile the design, create a SignalTap II File, and open the SignalTap II Logic Analyzer window.
Note: More information is available on running the SignalTap II Logic Analyzer on the Altera website.

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