| Understanding Assignment Priority | |
When you assign an entity to a LogicLock region, the assignment is inherited by all lower-level entities and nodes contained in that entity. If you assign an entity to a LogicLock region and assign one of its sub-entities or nodes to another LogicLock region, the more specific assignment on the sub-entity or node overrides the inherited assignment. For example, if you assign entity filter to LogicLock region LLR_0 and sub-entity filter|adder:my_adder to LogicLock region LLR_1, the sub-entity is placed in LLR_1, and all other sub-entities and nodes in filter are placed in LLR_0.
Some assignments in the Quartus® Prime Standard Edition software take precedence over LogicLock region assignments. When a node or entity has both a LogicLock region assignment and another assignment with a higher precedence, the Fitter ignores the LogicLock region assignment and produces a warning message. Types of assignments that take precedence over LogicLock region assignments include location Definition assignments and Fast Input Register, Fast Output Register, and Fast Output Enable Register logic options. The Fitter can ignore LogicLock region assignments on nodes or entities that require special physical resources, such as regional clock Definition, or pins with particular I/O standards.
LogicLock region assignments take precedence over the Optimize IOC Register Placement for Timing option available in the Advanced Settings(Synthesis) dialog box. However, for supported device(Arriaseries, Cycloneseries,MAX II, MAX V, andStratixseries) families, in the case of locked LogicLock regions that extend onto pins, the Fitter attempts to honor both the LogicLock region assignment and the Optimize IOC Register Placement for Timing option.