List of Messages |
CAUSE: In a Selected Signal Assignment at the specified location in a VHDL Design File (.vhd), you specified choices for a Selected Signal Assignment expression. However, the choices do not cover all possible values of the expression; as a result, errors may occur during the future processing of the design.
ACTION: Add choices for all possible values of the expression, or add an OTHERS choice, which covers all possible values that are not included in the other Selected Signal Assignment choices.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.