List of Messages |
always @(posedge clk or negedge reset) begin q <= data_in; endBecause the Always Construct does not contain any conditional logic to differentiate between clk and reset, the Quartus Prime software cannot identify the clock signal.
Naming has no impact when the Quartus Prime software identifies clock signals; the software identifies clock signals based only on the control flow in the Always Construct. |
ACTION: If you intended to infer a register for the Procedural Assignment, restructure the Always Construct to make the clock signal explicit. Refer to the Quartus Prime Help for information about correctly inferring synchronous logic using Verilog HDL. Otherwise, no action is required.
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