List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you declared a vector with more than 2**16 bits. The Verilog standard does not require tools to support vectors with more than 2**16 bits. Although Quartus Prime Integrated Synthesis supports your vector size, other Verilog tools may not. In addition, your design may require excessive amounts of logic depending on how you use this vector in statements and expressions.
ACTION: No action is required. To avoid receiving this message in the future, reduce the size of the vector, or declare the object as an array.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.