List of Messages |
CAUSE: In an expression at the specified location in a Verilog Design File (.v) you used a sized or unsized literal (a number). However, the width of the literal value in bits exceeds either the explicit size specified by you for a sized literal or the implicit size used by Quartus Prime Integrated Synthesis for unsized literals, which is guaranteed to be at least 32 bits. As a result, Quartus Prime Integrated Synthesis truncated the literal's value to match the specified number of bits.
ACTION: To avoid receiving this message in the future, edit the literal value so that it fits in the specified number of bits. You can either decrease the size of the literal value itself, or you can increase the explicitly declared size of the literal.
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