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signal data : std_logic; -- no default value signal foo : std_logic_vector(1 downto 0) := "01"; -- default value foo(1) <= data;In contrast, signal data (a scalar) has no assignment and no explicitly declared default value. Quartus Prime Integrated Synthesis will tie the net representing data to an implicit default value based on the signal's type. The implicit default value for a signal with scalar type T is T'LEFT, or the left-most value in the range of T. The implicit default value for a signal with type STD_LOGIC is U, a metalogical value which Quartus Prime Integrated Synthesis considers equivalent to X, a Don't Care value. (NOTE: Quartus Prime Integrated Synthesis does not generally treat X as a Don't Care during VHDL synthesis).
ACTION: No action is required. To remove the warning, assign an actual value to the net or give it an initial value of 1, 0, or Z.
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