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ENTITY example IS PORT ( b1 : INOUT BIT; b2 : INOUT BIT ); END example; ARCHITECTURE a OF example IS BEGIN b2 <= b1; END a;A directional assignment between bidirectional ports often represents an attempt to create a bidirectional connection between the two ports.
ACTION: If you intended for this behavior to occur, then no action is required. To remove the warning, redeclare the second bidirectional port as an output. However, if you truly require a bidirectional connection between the two ports, then you will need to revise your design. In Verilog, you may use the tran primitive to create such a connection. In VHDL, such connections are effectively impossible.
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