List of Messages |
CAUSE: The specified net in the post-elaboration (unoptimized) netlist exceeds the specified HDL fan-out limit, which you set via the HDL Fan-out Limit logic option.
ACTION: Consider reducing the fan-out of the specified net by manually duplicating its driving logic cone and distributing the fan-out among the duplicate cones. You can also use the maxfan synthesis attribute in Verilog HDL or VHDLto force the Quartus Prime software to duplicate the driver and split the fan-out automatically. If you do not want to split the fan-out, consider using the GLOBAL Primitive to drive the specified net in your HDL source. When driven by this primitive, the specified net is routed by the Quartus Prime software using a global routing resource, depending on the target device family and the available routing resources.
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