List of Messages |
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you attempted to create the specified synthesis attribute. However, the value you tried to assign is not a valid value for that specific synthesis attribute. As a result, this setting is ignored.
ACTION: Many synthesis attributes only accept a small set of specific values, or a particular value format. Check the value you are assigning to the specific synthesis attribute against the values accepted by that attribute.
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