List of Messages |
CAUSE: In a VHDL Design File (.vhd) at the specified location, you compared two composite types with different lengths. When you use a pre-defined VHDL comparison operator, Quartus Prime Integrated Synthesis considers operands with unequal lengths as unequal. Therefore, the result of the comparison is always TRUE (if you are testing for inequality) or FALSE (if you are testing for equality).
ACTION: If you expected this behavior, no action is required. Otherwise, check the sizes and types of the operands. You may want to resize the smaller operand manually, or change the types of the operands to utilize an overloaded comparison function that behaves as you intended. For example, the unsigned type in numeric_std has an overloaded comparison function that zero-extends operands as necessary to match the operand sizes.
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