List of Messages |
CAUSE: In a Verilog Design File (.v) , you connected the specified formal port on a module to an actual expression whose size does not match the size of the formal port. If the specified port is wider than the expression, then some bits in the port will be left unconnected.
ACTION: If the mismatched part of the connected ports does not cause a problem in the design, you may ignore this message. Otherwise, make sure the connected ports are of the same size.
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