List of Messages |
CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you instantiated a module, but specified some of the port connections in ordered form, and others in named form. Port connections must be all by order or all by name; the two types cannot be mixed.
ACTION: Connect the ports in the Module Instantiation either all by name or all by order.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.