List of Messages |
CAUSE: In a Verilog Design File (.v) at the specified location, you declared an array with more than 2**24 bits. The Verilog language does not require tools to support arrays with more than 2**24 bits. Although Quartus Prime Integrated Synthesis supports arrays with more than 2**24 bits, your design may require excessive amounts of logic unless Integrated Synthesis can map the array into an inferred RAM.
ACTION: No action is required. To avoid receiving this message in the future, reduce the bit size of the array.
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