List of Messages |
CAUSE: In a Verilog Design File (.v), you attempted to implement a state machine using the specified state register. However, by analyzing the register's next-state logic, Quartus Prime Integrated Synthesis determined that the register is too small to store all the state machine's possible states; for example, Quartus Prime Integrated Synthesis may have determined that the next-state logic assigns more than 2^N distinct values to the N-bit register. To preserve the functionality of the Verilog HDL source as written, Quartus Prime Integrated Synthesis cannot extract a state machine from the register.
ACTION: Increase the state register's bit width and/or modify the register's next-state logic.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.