List of Messages |
CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you used a UDP table that is empty. As a result, Integrated Syntheses will create an empty primitive gate.
ACTION: No action is required. To avoid receiving this message in the future, enter the correct logic function information into the UDP table.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.