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reg data, enable, bad_latch; always@( data && enable ) begin bad_latch = data; endA Verilog simulator executes the Always Construct whenever the value of the expression (data && enable) changes value, effectively creating a pseudo-latch. Quartus Prime Integrated Synthesis, however, ignores the pseudo-latch behavior implied by the Event Control and implements purely combinational logic for the Always Construct.
reg data, enable, good_latch; always@( data or enable ) begin if(enable) good_latch = data; end
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