List of Messages
Parent topic: List of Messages

ID:17200 Verilog HDL warning at <location>: name of port declaration in module definition does not match that in extern module

CAUSE: Quartus Prime Integrated Synthesis generated the specified warning message for the specified location in a Design File.

ACTION: No action is required. To remove the warning, address the issue identified by the message text. A future version of the Quartus Prime software will provide more extensive Help for this warning message.

Parent topic: List of Messages

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