List of Messages |
CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you attempted to specify pin assignments for the elements of the specified port using the chip_pin or altera_chip_pin_lc synthesis attribute. However, the pin assignment list for the synthesis attribute contains the specified number of pin assignments, which is too few or too many pin assignments for the port. The number of pin assignments must match the specified bit width of the port. As a result, Quartus Prime Integrated Synthesis ignored the synthesis attribute.
attribute chip_pin : string; attribute chip_pin of a : signal is "1, , 2";
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