List of Messages |
CAUSE: The specified Verilog Design File (.v) or VHDL Design File (.vhd) contains the MESSAGE_ON or the MESSAGE_OFF directive, followed by a message ID; however, the specified message ID is not an HDL message ID - that is, it is not between 10000 and 11000.This is not allowed. MESSAGE_ON and MESSAGE_OFF directives can only accept HDL message IDs. As a result, Quartus Prime Analysis & Synthesis will ignore the specified ID.
ACTION: Either specify an HDL message ID with the MESSAGE_ON or the MESSAGE_OFF directive, or use a MESSAGE_ENABLE or MESSAGE_DISABLE attribute for non-HDL messages.
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