List of Messages |
CAUSE: In a Verilog Design File (.v), you used an expression, possibly a constant literal, that was extended. However, the most-significant bit (the sign bit if this expression was a signed expression) of the expression was "x" or "z". As a result, the number was extended with "x" or "z" bits, which may or may not be what you intended to occur.
ACTION: If you intended this behavior to occur, then no action is required. Otherwise, modify the expression or constant so that the most-significant bit is not "x" or "z".
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.