List of Messages |
CAUSE: In a Verilog Design File (.v), you used a multi-bit expression in a condition expression. Quartus Prime Integrated Synthesis will reductively OR the bits in the expression together to form the conditional signal.
ACTION: If you intended to use a multi-bit expression in a condition expression, then no action is required. Otherwise, revise the expression so that it evaluates to a single bit.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.