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CAUSE: In an always construct in a Verilog Design File (.v), you mixed blocking and non-blocking assignments. Although Verilog HDL permits you to mix both types of assignments, doing so can introduce subtle bugs into your HDL source; it can also introduce differences between the simulated behavior of the design and the synthesized netlist. In general, you should use blocking assignments in always constructs that model combinational logic and non-blocking assignments in always construct that model sequential logic.
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