List of Messages |
CAUSE: At the specified location in a Verilog Design File (.v), you used the parallel_case synthesis attribute in a Case Statement that does not contain mutually exclusive case item expressions. The parallel_case synthesis attribute directs Analysis & Synthesis to implement parallel logic rather than a priority scheme for all case item expressions in the Case Statement. Analysis & Synthesis implemented the parallel_case synthesis attribute; however, in doing so, Analysis & Synthesis may have created synthesized logic for the current design with functionality that differs from the functionality you simulated for the design.
ACTION: Check the synthesized logic for design integrity.
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