List of Messages |
CAUSE: In a Verilog Design File (.v), you redefined the specified macro. The remainder of the design will use the new macro definition until you redefine the macro again.
ACTION: No action is required. To prevent this warning in the future, use a different macro name for each new definition. This often results in a clearer, more robust design.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.