List of Messages |
CAUSE: In a case statement at the specified location in a Verilog Design File (.v), you specified the full_case synthesis attribute on a case statement with a default case item. Quartus Prime Integrated Synthesis ignored the full_case synthesis attribute as redundant.
ACTION: No action is required. To eliminate the warning, remove the full_case synthesis attribute or remove the default case item.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.