List of Messages |
CAUSE: At the specified location in a Verilog Design File (.v), you used the full_case synthesis attribute in a Case Statement that does not contain all possible state values or a Default Statement. The full_case synthesis attribute directs Analysis & Synthesis to treat unspecified state values in the Case Statement as Don't Care values. Analysis & Synthesis implemented the full_case synthesis attribute; however, in doing so, Analysis & Synthesis may have created synthesized logic for the current design with functionality that differs from the functionality that you simulated for the design.
ACTION: If possible, change the Case Statement so it is "full," that is, all the state values in the Case Statement are specified or the Case Statement contains a Default Statement. You can then remove the full_case synthesis attribute from the Case Statement.
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