List of Messages |
CAUSE: In an assignment at the specified location in a Verilog Design File (.v), you assigned a value to a target whose size (given in parentheses) is too small to store the entire value. As a result, Quartus Prime Integrated Synthesis truncated the value to match the size of the target.
ACTION: If this behavior is correct, then no action is required. Otherwise, to avoid receiving this message in the future, increase the size of the target or decrease the size of the assigned value until both target and assigned value have the same size.
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