List of Messages |
CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you declared the specified object. Later on, you assigned a value to this object, but you never read the value of this object in an expression, port connection, and so on.
ACTION: If you intended to leave the object assigned but unread, no action is required, although you may prevent this message in the future by removing the object from the design. Otherwise, check the design for mistakes.
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