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CAUSE: The Fitter has detected regions in the device with high HCell utilization. You can use HCells to implement design logic, as well as to buffer routed signals. The HardCopy Design Center back-end flow requires unused HCells for buffering test signals, as well to facilitate targeted design re-optimization. If you use a significant number of regions, back-end processing time for this design may increase.
ACTION: LogicLock regions containing a large amount of design logic may prevent the Fitter from spreading out sufficiently to ensure an adequate number of unused HCells. Review any LogicLock regions in the design and increase their size if they appear highly utilized in the Chip Planner. Additionally, you may use HCells to add delay to satisfy hold requirements in the design. For transfers requiring significant delay insertion , review the "Estimated Delay Added for Hold Timing" section of the Fitter report. If such transfers exist, verify that the timing constraints, especially multicycles, are set properly. Avoid using gated clocking whenever possible. If these actions do not reduce the HCell utilization, contact the HardCopy Design Center for further actions.
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