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CAUSE: The TimeQuest Timing Analyzer found latches implemented using non-optimal resources (look-up tables (LUTs) with combinational feedback). The TimeQuest analyzer replaces the combinational loop with an equivalent latch. The TimeQuest analyzer treats this logic as a synchronous endpoint, and will not analyze the path through the node.
ACTION: You must implement these latches with registers using asynchronous load and data signals, or remove them from your design. For more information, run the check_timing tcl command in the TimeQuest analyzer.
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