List of Messages |
CAUSE: Base clock for the PLL couldn't be derived because frequency setting for the PLL couldn't be found.
ACTION: You can manually create the base clock for the PLL.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.