ID:12125 Using design file <name>, which is not specified as a design file for the current project, but contains definitions for <number> design units and <number> entities in project

CAUSE: You used the specified number of design units and entities in the current project. Analysis & Synthesis is using the specified design file to determine the definitions of the design units and entities, even though you have not added the design file to the project.

Analysis & Synthesis selects the design file it uses based on design file type, in the following order of preference:

EDIF Input File ( .edf)
Verilog Quartus Mapping File ( .vqm)
Text Design File ( .tdf)
Verilog Design File ( .v)
VHDL Design File ( .vhd)
Block Design File ( .bdf)
Graphic Design File ( .gdf)

ACTION: If you want Analysis & Synthesis to use a different design file, if you want to avoid problems in the future processing of the design, or if you want to avoid receiving this message in the future, add the design file you want Analysis & Synthesis to use to the project. Otherwise, no action is required.