List of Messages
Parent topic: List of Messages

ID:12089 PLL will not be created from CLKLOCKx1 Input Frequency logic option when generating functional simulation netlist

CAUSE: You set the PLL.

ACTION: No action is required.

Parent topic: List of Messages

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.