ID:218006 Current setting of the Programmable Power Technology Optimization logic option forces all tiles with failing timing paths to high speed

CAUSE: This warning message indicates that the Fitter is forcing tiles with failing timing paths to high speed. Using high-speed tiles on failing timing paths can help you diagnose timing closure problems that must be resolved with design or CAD settings changes. However, doing so will increases static power consumption.

ACTION: After you close timing, recompile the design. Because the high-speed tile use may be reduced, rerun the PowerPlay Power Analyzer to obtain an accurate estimate of the power requirements.