List of Messages |
module test1 (input oe1, data1, in, output out); wire tribuf, tmp; assign tribuf = oe1 ? data1 : 1'bz; and(tmp, in, tribuf); assign out = tmp; endmoduleHere, the tri-state buffer tribuf only drives a non-tri-state node (the AND gate). As a result, the tri-state buffer will be converted to a wire. Note that an inversion also counts as non-tri-state logic. So, the node tribuf in the design test2 will also be converted to a wire.
module test2 (input oe1, data1, output out); wire tribuf; assign tribuf = oe1 ? data1 : 1'bz; assign out = !tribuf; endmodule
ACTION: Avoid this warning by replacing the tri-state node with non-tri-state logic.
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.