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module test1 (input oe1, data1, oe2, data2, in, output out); wire triwire, tmp; assign triwire = oe1 ? data1 : 1'bz; assign triwire = oe2 ? data2 : 1'bz; and(tmp, in, triwire); assign out = tmp; endmodule
ACTION: Avoid this warning by replacing the tri-state node with a non-tri-state logic.
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