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module test1 (input oe1, data1, in, output out, inout bidir); wire tribuf, tmp; assign tribuf = oe1 ? data1 : 1'bz; and(tmp, in, tribuf); assign bidir = tribuf; assign out = tmp; endmoduleHere, the tri-state buffer tribuf has fan-outs to both the tri-state and non-tri-state nodes. As a result, the fan-out to the non-tri-state node is converted to !oe1 + data1. Note that an inversion also counts as non-tri-state logic. So, the node tribuf in the design test2 is also converted to an OR gate.
module test2 (input oe1, data1, output out, inout bidir); wire tribuf; assign tribuf = oe1 ? data1 : 1'bz; assign bidir = tribuf; assign out = !tribuf; endmoduleAdditionally, a tri-state buffer feeding the output enable signal of another tri-state buffer is also converted to logic. Consider the following Verilog design:
module test3 (input oe1, data1, data2, inout bidir); wire tribuf1, tribuf2; assign tribuf1 = oe1 ? data1 : 1'bz; assign tribuf2 = tribuf1 ? data2 : 1'bz; assign bidir = tribuf2; endmoduleHere, the tri-state buffer tribuf1 is converted to an OR gate.
ACTION: Avoid this warning by either removing the non-tri-state fan-out of the tri-state buffer or replacing the tri-state buffer with non-tri-state logic.
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