List of Messages |
CAUSE: Your design includes pins for which you specified a custom capacitive load that differs from the Quartus Prime default for the assigned I/O standard. As a result, the delay introduced by this capacitive load will be overestimated when combining Quartus Prime and IBIS predicted delays.
ACTION: To correctly interface Quartus Prime timing and IBIS simulations, you will have to revert to the default capacitive loads.
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