List of Messages |
CAUSE: Your design includes pins for which you specified a custom board trace model that differs from the Quartus Prime default for the assigned I/O standard. As a result, the delay introduced by this board trace model may be over- or underestimated when combining Quartus Prime and IBIS predicted delays.
ACTION: To correctly interface Quartus Prime timing and IBIS simulations, revert to the default board trace model.
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