ID:196002 Run Analysis and Synthesis (quartus_map) with top-level entity name <Top-level entity name> before running EDA Netlist Writer to generate HSPICE Simulation Deck file

CAUSE: You used the Compiler to generate an HSPICE Simulation Deck file (.sp) for performing board-level signal integrity verification of Altera devices with other EDA tools. However, without running Analysis & Synthesis, the Quartus Prime software cannot generate the HSPICE Simulation Deck file for all user pins.

ACTION: No action is required.