ID:196007 <number> pins have non-default I/O load assignment(s). This will result in a mismatch between HSPICE predicted delay and Quartus reported delay.

CAUSE: Your design includes pins for which you've specified a custom capacitive load that differs from the Quartus Prime default for the assigned I/O standard. As a result, the delay introduced by this capacitive load will be overestimated when combining Quartus Prime and HSPICE predicted delays.

ACTION: To correctly interface Quartus Prime timing and HSPICE simulations, you will have to revert to the default capacitive loads.