List of Messages |
CAUSE: Altera does not recommend using the FPGA to HPS SDRAM PLL, since it could be subject to jitter.
ACTION: Disconnect the FPGA to HPS SDRAM PLL (f2h_sdram_ref_clk) and use the one of the HPS dedicated Clock pins as a reference clock instead (HPS-CLK1 or HPS-CLK2)
Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.